Cantata Test Architect Webinar
Cantata Test Architect enables you to rapidly isolate and remediate architectural issues. It gives software engineers a fast and visual way to represent an application’s structure with its unique Dependency Structure Matrix. This gives insight into how different software layers interact and can identify test surfaces to help exercise the code and achieve your coverage goal when working towards industry standards.
In this introductory online presentation, Adam Mackay the Integrations Manager of QA Systems in the UK, introduces the Cantata Test Architect Webinar.
Using Cantata Test Architect Adam shows how to break down a complex system into its component parts, identify dependencies, and plan distinct sub-projects – easing the burden of test set-up.
I/O with CANopen and CANopen FD for Industrial Use
In cooperation with the partner Embedded Systems Academy (EmSA), PEAK-System has developed an I/O device with CANopen and CANopen FD connection. The PCAN-MicroMod FD DR CANopen Digital 1 has 8 digital inputs and 8 digital outputs and is delivered in a DIN rail housing with Phoenix screw terminal strips.
The inputs comply with the PLC standard DIN EN 61131-2 and have a Type 3 characteristic; they are galvanically isolated in two groups up to 100 V from the device supply.
The digital outputs on high-side switch basis can each be loaded up to 500 mA. Mechanisms such as thermal protection, short-circuit detection, and open-load detection increase the reliability of the outputs.
The Node ID and bit rates are set via rotary switches. This allows the device to be set up for use in new CANopen FD and classic CANopen networks without additional configuration software. CANopen conformity has been tested and certified by the CAN in Automation (CiA) association.
The device conformity test and certification for CANopen FD® is pending.
Ny version av CodeSonar, 5.3
Den senaste versionen av GrammaTech CodeSonar, version 5.3, har flera nya funktioner såväl som kompatibilitetsuppdateringar och andra förbättringar.
Denna version inkluderar förbättringar i stöd för Android, NetBSD 8, Visual Studio 19, CWE 4.0, samt utökat stöd för MISRA-C, MISRA-C ++ och AUTOSAR C ++ 14 regler.
TRACE32 supports SDMA in i.MX Application Processors
Lauterbach are pleased to announce support for the SDMA engine in the NXP iMX family of processors. The IMX devices are designed for demanding applications in various fields, including Automotive, Avionics and Transport, Robotics, Building Control, Healthcare, and General HMI solutions.
This feature will be available from the 2nd May 2020 to Lauterbach customers. Initially, support for iMX6 is included but this will be extended to support other iMX devices.
Free Micro CANopen Libraries for NXP Microcontrollers
Embedded Systems Academy (EmSA) and NXP® Semiconductors announce the integration of the free-to-use EmSA Micro CANopen libraries into the NXP MCUXpresso Software Development Kit (SDK) for developing with NXP’s microcontrollers (MCU) and crossovers based on Arm® Cortex®-M.
For more information about the NXP microcontrollers currently supported by EmSA’s free to use CANopen libraries and video tutorials, visit www.em-sa.com/nxp
OS and RTE Profiling for TriCore™ AURIX™
Vector and Lauterbach have jointly developed a solution for Vector’s AUTOSAR classic basic software MICROSAR. The main idea is to configure trace hooks in such a way that trace data with timestamps are generated for all task switches, all task state changes, all ISR events, and all Runnable starts/ends.
TRACE32 and Python
With the improved Python support we want to enhance two main areas:
• The Remote API in Python enables test frame developers to run complex tests via a
TRACE32 backend using a native Python script (see picture to the left).
• The new ability to edit and run Python scripts in TRACE32 gives developers direct
access to features from the Python scripting environment (see picture to the right).
SEGGER releases Floating-Point Library for RISC-V
SEGGER’s stand-alone Floating-Point Library is now extended by an assembly-optimized variant for RISC-V.
The floating-point library contains the complete set of arithmetic functions, hand coded and fully optimized in assembly language for RISC-V. The complete set of high-level mathematical functions is written in C, and uses advanced algorithms to maximize performance.
All functionality is fully verified, for both single and double precision operations.
The RISC-V variant, like the variant for ARM, is optimized for both high speed and small code size. The balance between size and speed can be configured at library build time. The SEGGER Floating-Point Library for RISC-V is much smaller than equivalent open-source libraries while achieving up to 100 times the performance on some operations.
Addition of support for NXP S32G
Lauterbach, the world’s leading debug tools provider, is pleased to announce the addition of support for the NXP S32G Vehicle Network Processor family to their TRACE32 debug and trace tools. The S32G family provides hardware security, ASIL D safety and high-performance processing for a range of automotiveapplications.